I. Field of the Disclosure
The technology of the disclosure relates generally to memory management units (MMUs) of computer processing systems.
II. Background
Memory management units, or MMUs, are elements of modern computer processing systems that provide memory management functionality to computer processors and/or peripheral devices. Such memory management functionality may include virtual-to-physical memory address translation and caching, as well as memory protection and attribute control. As the number of processing cores in modern computer processors has increased, the amount of processor chip area that is dedicated to providing MMU functionality to those processing cores has likewise increased.
The MMU architectures presently known in the art have proven ineffective in reducing the chip area cost of providing MMU functionality while maintaining MMU performance. One such architecture is referred to herein as a “monolithic MMU” architecture. A computer processing system employing a monolithic MMU architecture provides multiple monolithic MMUs, each of which includes one input data path and one output data path. Each monolithic MMU also provides its own translation cache and transaction buffer and scheduler, and one or more dedicated hardware page table walkers. Because each of the monolithic MMUs operates independently of the other monolithic MMUs, high processing performance may be achieved by providing one MMU for each high-performance traffic-producing client. However, the monolithic MMUs may consume a relatively large chip area due to the duplication of their constituent elements, and sharing of a monolithic MMU among low-performing clients may result in performance degradation.
Another MMU architecture is referred to herein as the “distributed MMU” architecture. In a computer processing system employing a distributed MMU architecture, each traffic-producing client may be associated with a corresponding client MMU unit. Each client MMU unit provides a local transaction buffer and scheduler and a local translation cache for its associated traffic-producing client. The client MMU units are communicatively coupled to a central MMU unit, which provides a central translation cache and one or more hardware page table walkers. Because the hardware page table walker(s) of the central MMU unit are shared between the client MMU units, the distributed MMU architecture may provide chip area savings relative to monolithic MMUs for lower-performance processors. However, the distributed MMU architecture does not scale well to mid- and high-performance processors. This is due in part to replication of translation cache entries in the client MMU units and the central MMU unit, as well as the chip area required for interconnects between each client MMU unit and the central MMU unit. The central MMU unit may also require a dedicated port to a memory controller interconnect, which may further increase chip area used.